USB4 Version 2.0 - Link Configurations
November 6, 2023
USB4 Version 2.0 specification was released by the USB Promoter Group earlier this year. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.
The new version brings with it the possibility of configuring the USB4 link in asymmetric mode or transitioning to it from the symmetric mode.
There are a few changes in the terminologies as well for describing a USB4 link. The term Dual-Lane is no longer used. Instead, a USB4 link that uses two bonded lanes to transmit and receive data is called an Aggregated Link, which can be a Symmetric Link or an Asymmetric Link.
To read the full article, click here
Related Semiconductor IP
- USB4 Gen3 x2-lane PHY, TSMC N5, 1.2V, N/S orientation, type-C
- USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
- USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
- USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
- USB4 PHY - SS SF2, North/South Poly Orientation
Related Blogs
- USB4 Version 2.0 - Low Power with Gen4 Link
- USB4 Version 2.0 - Gen4 Link Recovery
- USB4 Version 2.0 - Gen4 High-Speed Lane Initialization and Training
- Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing