USB4 Version 2.0 - Low Power with Gen4 Link
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80 Gbps link speed per direction in symmetric mode and 120 Gbps link speed in asymmetric mode.
Here, we take an overview of the low power entry and exit flows in Gen4 link speed and how they have been simplified as compared to that in Gen2/Gen3 link speed.
In Gen4, the low power entry has been made uni-directional, which means that there is no need for an ACK handshake anymore, hence removing any dependency on the link partner. The low power can be symmetric (CL1 or CL2) or asymmetric (CL0s). Only CL_OFF Ordered Sets are used to enter a low power state (CL0s, CL1, CL2). Now, CL1 and CL2 can be entered only from CL0s.
Related Semiconductor IP
- USB4 Gen3 x2-lane PHY, TSMC 12FFC, 1.8V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N7, 1.8V or 1.2V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N5, 1.2V, N/S orientation, type-C
- USB4 Controller & Router IP
Related Blogs
- USB4 Version 2.0 - Gen4 High-Speed Lane Initialization and Training
- USB4 Version 2.0 - Link Configurations
- USB4 Version 2.0 - Gen4 Link Recovery
- Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?