USB4 Version 2.0 - Gen4 Link Recovery
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.
Here, we take an overview of the Gen4 link recovery mechanism, which is an autonomous process. It is initiated by a router when it encounters uncorrectable error events. These error events could be a timeout error, de-skew buffer error, or RS-FEC decode error.
Gen4 link recovery uses the newly defined ELT_recovery transaction of the sideband channel. This transaction is used for both Gen4 Link Recovery initiation and completion.
A router sends ELT_recovery transaction if there is an error case that requires Gen4 link recovery, or it receives ELT_recovery transaction, or ‘Initiate Gen 4 Link Recovery’ bit in PORT_CS_19 is set to ‘b1.
Gen4 link recovery preserves the current configuration space and the router states. It would also stop time-sync handshakes and transport layer scheduling, but other than that, it would stop idle packets.
An ELT_recovery transaction is sent on the sideband channel to the other router. When the other router receives this ELT_Recovery transaction, it also sends an ELT_Recovery Transaction back to the initiating router.
Related Semiconductor IP
- USB4 Gen3 x2-lane PHY, TSMC 12FFC, 1.8V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N7, 1.8V or 1.2V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
- USB4 Gen3 x2-lane PHY, TSMC N5, 1.2V, N/S orientation, type-C
- USB4 Controller & Router IP
Related Blogs
- USB4 Version 2.0 - Low Power with Gen4 Link
- USB4 Version 2.0 - Gen4 High-Speed Lane Initialization and Training
- USB4 Version 2.0 - Link Configurations
- Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?