USB4 PHY - SS SF2, North/South Poly Orientation

Overview

The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the leading process technologies such as 5nm FinFET. The USB4 PHYs use a single efficient GDSII design that supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates.

The USB4 IP is designed to meet the functionality, power, performance, and area requirements of a broad range of storage, PC, and tablet SoC designs as well as software development debug and easy deployment of artificial intelligence (AI) applications at the edge.

The USB IP has shipped in billions of units for leading electronics companies worldwide. Using the USB IP significantly reduces development time and engineering risk, helping designers to bring USB-based SoCs to market faster.

The USB IP is the most certified IP solution in the industry. As the leading provider of USB IP for nearly two decades, the vendor is enabling designers to lower the risk and adoption barrier of integrating USB4 functionality into their SoCs.

Key Features

  • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
  • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
  • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
  • Low active and standby power
  • Small area for low silicon cost
  • USB Type-C connectivity support available (external party Type-C Port Controller not included)

Block Diagram

USB4 PHY - SS SF2, North/South Poly Orientation Block Diagram

Technical Specifications

Foundry, Node
SS SF2, North/South Poly Orientation
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Semiconductor IP