Scaling AI Chip Design With NoC Soft Tiling

By Andy Nightingale, Arteris

Repetition of modular units inside a network-on-chip facilitates scalability and reusability.

Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon pieces to achieve a more diverse and powerful system within a single package.

Network-on-chip (NoC) soft tiling is complimentary but distinct from chiplets described above as it repeats modular units inside a NoC design. Soft tiling within a NoC offers scalability and reusability, making it ideal for automotive, communications, enterprise computing and consumer electronics system-on-chip (SoC) designs.

One example of soft tiling is in advanced driver-assistance systems (ADAS) in automotive applications, where real-time data is managed for AI-driven object detection and decision-making. In another example from the data center vertical, soft tiling facilitates the scaling of AI accelerators, enabling systems to handle data-intensive tasks such as large language model (LLM) training and generative AI.

As the demand for AI applications expands across multiple industries, semiconductor designers are rethinking traditional chip architecture. Requirements for higher computational power, energy efficiency, area optimization and faster deployment have made it clear that conventional design methods are no longer sufficient to meet the complexities of AI workloads. Soft tiling, an innovative solution in NoC designs, addresses two main challenges in system-on-chip (SoC) development. First, it allows for scalable, modular designs where each soft tile can be duplicated across the SoC without redesign. Second, it offers significant benefits for derivative designs, enabling the reuse of pre-verified tiles, which reduces design time, complexity and area constraints.

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