SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout.
Performance (throughput and latency) optimized non-coherent NoC solution that significantly reduces silicon wire utilization, resulting in power and area efficient ICs.
SkyeChip’s Non-Coherent Network-on-Chip (NoC) IP works together with SkyeChip’s Resource and Performance Tuner (RAPTuner ™) to deliver system-optimized interconnect solutions that is used in the
construction of ASICs, SoCs, FPGAs and ASSPs.
Non-Coherent Network-on-Chip (NoC)
Overview
Key Features
- External Interface Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
- Architected to reduce routing congestion and to ease high frequency timing closure
- Supports operating frequencies up to 2GHz
- Supports source synchronous and synchronous clocking topologies
- Supports 2.5D and 3D die-to-die NoC bridging
- Integrates seamlessly with SkyeChip’s Non-Coherent NoC for partitioned interconnect systems
Benefits
- Deadlock-Free Routing
- Synchronous, Asynchronous & Source-Synchronous Clock
- Configurability & Debug
Deliverables
- RAPTuner ™ software
- Software user manual
- NoC IP Core
- Documentation
Technical Specifications
Availability
Since April 2024