FlexNoC 5 Interconnect IP

Overview

Physically Aware Network-on-Chip IP

The latest generation FlexNoC 5 Interconnect with its integrated physical awareness technology, gives place and route teams a much better starting point while simultaneously reducing interconnect area and power consumption. FlexNoC 5 delivers up to 5X shorter turn-around-time versus manual physical iterations.

The combined use of FlexNoC and Ncore IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.

Key Features

Auto-timing closure assist
NIU (Network Interface Unit) tiling to organize NIUs into modular, repeatable blocks, improving scalability, efficiency, and reliability
Topology visualized directly on floorplan
Multi-clock/power/voltage domains and power management with unit-level clock gating
Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter Enumerations
General optimizations for lower area e.g. up to 30% for some NoC elements depending on configuration
Native and user-defined firewall security
Import and export to Magillem tools
AMBA 5 support of DVM 8.1 (Distributed Virtual Memory)
On-chip performance monitoring and debug
Debug and trace with ATB 128b and timestamps

Benefits

Flexible Topologies
- FlexNoC is generated from simple elementary components which are combined by a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.
Small to Large SoCs
- FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.
Huge Bandwidth
- FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multi-channel HBMx memory and high bandwidth data paths.

Block Diagram

Video

Arteris FlexNoC 5 Physically Aware Network-on-Chip IP

Arteris unveils next-generation FlexNoC 5 physically aware network-on-chip IP. Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.

Applications

Automotive,
Mobility,
Wireless,
Consumer Electronics,
IoT,
Server,
Networking and Industrial SoCs

Deliverables

FlexNoC 5 Physically Aware Interconnect IP
Configuration tools
Automated testbench generator
Documentation, training, and support.
Safety Manual -- when licensed with the Functional Safety (FuSa) Option

Technical Specifications

Foundry, Node

all

Maturity

FlexNoC shipping in production chips

Availability

FlexNoC 4 available now, FlexNoC5 in early access programme

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