Optimizing Electronics Design With AI Co-Pilots
By Ben Gu, Cadence
EETimes (November 27, 2023)
Design processes are evolving rapidly, and their use will enable the highly optimized ICs, PCBs and systems that we need to keep global innovation on track. Today’s efforts to apply analysis much earlier in the design exploration and validation process are already enabling complex multiphysics analyses and co-optimization across domains. However, increasing design complexity means we may soon need to move beyond such in-design analysis—to processes enabled by machine learning (ML) and AI.
This may sound like a reach, but ML techniques are clearly very powerful, if applied intelligently, and the one thing that the electronics industry is never short of is design data. Surely there must be a thoughtful way to bring them together.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Revolutionizing Consumer Electronics with the power of AI Integration
- Scaling AI Chip Design With NoC Soft Tiling
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- Revolutionizing Chip Design with AI-Driven EDA
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks