Optimizing Electronics Design With AI Co-Pilots
By Ben Gu, Cadence
EETimes (November 27, 2023)
Design processes are evolving rapidly, and their use will enable the highly optimized ICs, PCBs and systems that we need to keep global innovation on track. Today’s efforts to apply analysis much earlier in the design exploration and validation process are already enabling complex multiphysics analyses and co-optimization across domains. However, increasing design complexity means we may soon need to move beyond such in-design analysis—to processes enabled by machine learning (ML) and AI.
This may sound like a reach, but ML techniques are clearly very powerful, if applied intelligently, and the one thing that the electronics industry is never short of is design data. Surely there must be a thoughtful way to bring them together.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- Revolutionizing Consumer Electronics with the power of AI Integration
- Scaling AI Chip Design With NoC Soft Tiling
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- Revolutionizing Chip Design with AI-Driven EDA
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension