NoC System IP

Overview

The Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs.

With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce challenges to physical designs, specifically when routing large numbers of wires and meeting clock speed targets.

The Janus NoC addresses those challenges by employing multiple strategies:

Packetization allows a reduction of the wire count
Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster

Key Features

Reduces wire count and congestion
Reduces physical design issues
Handles gear change automatically
Configurable to meet your PPA goals
Easy to configure with a quick turnaround of configuration changes
Use with Cadence simulation/emulation to identify bottlenecks and remove them

Benefits

Intuitive Design Entry Tool
- Use a powerful GUI to generate a NoC configuration, then submit the configuration to get RTL and SystemC models
Highly Configurable
- Configure BW, latency, clock domain crossings, clock gating, buffer size, and pipeline stages—everything you need to achieve your target PPA goals
Scalability
- Start with subsystem design, then take the same design and create a full SoC; Need a higher level of integration? No problem, we can do chiplets as well

Block Diagram

Technical Specifications

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