What's New With Cadence PCI Express IP? Almost Everything!
PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this year where several hundred customers from more than a hundred unique companies visited the conference. The next-generation PCI Express (PCIe) 5.0 specification was announced with plans for ratification in 2019. The announcement had a supporting quote by Cadence confirming our long-term commitment to developing products for PCIe interface protocols. The schedule for adoption of the new standard has been accelerated to less than 2 years to keep up with the networking and storage throughput requirements of the data center. The PCIe 4.0 specification v0.9 was also released and is expected to be ratified later this year.
The Cadence PCIe 4.0 integrated PHY and Controller IP solution had a good showing at a demo of x16 16Gbps PCIe PHY based on 16nm running at speeds over 22Gbps and the complete PCIe 4.0 solution (PHY+Controller) interoperating with a Mellanox end-point.
To read the full article, click here
Related Semiconductor IP
- Multi-Channel Flex DMA IP Core for PCI Express
- PCIe - PCI Express Controller
- PCI Express PIPE PHY Transceiver
- Scalable Switch Intel® FPGA IP for PCI Express
- Multichannel DMA Intel FPGA IP for PCI Express*
Related Blogs
- Navigating the Complexity of Address Translation Verification in PCI Express 6.0
- Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
- Understanding PCIe 6.0 Shared Flow Control
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
Latest Blogs
- Securing The Road Ahead: MACsec Compliant For Automotive Use
- Beyond design automation: How we manage processor IP variants with Codasip Studio
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding