PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up
Two articles from EETimes give an exciting picture for PCI Express’ short- and long-term future. On the most immediate front, 23 adapter cards and 19 systems from PC and peripheral makers participated in the most recent PCIe Gen 3 plugfests. These are prototypes so it’s still early days for this interface standard, which moves data at 8 Gtransfers/sec. There are still many more chips, boards and systems to be designed using the PCIe Gen 3 standard. One of the two articles quotes Ramin Neshanti, chairman of the PCI SIG‘s serial communications working group, as saying “PCI Express Gen 3 is more sophisticated in its electrical design [than past PCI SIG standards], so we are giving members more feedback on how they are doing” with their first products. (Just a side note: PCIe Gen 3 designs clearly benefit from thorough verification before silicon implementation. To do that, you need good verification IP.)
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
- PCIe 6.0 - All you need to know about PCI Express Gen6
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
- Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing