Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector. We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors – by far the main attraction of DevCon this year.
As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.
To read the full article, click here
Related Semiconductor IP
- PCIe 7.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
- PCIe 7.0 PHY, TSMC N3P x4, North/South (vertical) poly orientation
- PCIe 7.0 PHY, TSMC N2P x4, North/South (vertical) poly orientation
- PCIe 7.0 PHY, TSMC Intel 18A x4, North/South (vertical) poly orientation
- PCIe 7.0 PHY in TSMC (N5, N3P)
Related Blogs
- Understanding PCIe 6.0 Shared Flow Control
- Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon 24
- Industry's First Verification IP for PCIe 7.0
- Industry's First Adopted VIP for PCIe 7.0
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview