The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 64 downstream ports.
Scalable Switch Intel® FPGA IP for PCI Express
Overview
Key Features
- Switch Upstream / Downstream Port
- Configurations
- PCIe 3.0 x4/x8/x16
- PCIe 4.0 x4/x8/x16
- PCIe 5.0 x4/x8/x16
- 1 PF for Upstream Port / 1 PF per Downstream Port
- Single Upstream Port
- Up to 96 Downstream Embedded Endpoints (E-EP)
- Up to 32 Downstream Discrete Endpoints (D-EP)
- Configurations
- Switch Downstream Port
- Static device number allocation
- Supports Alternative Routing ID (ARI) forwarding for Discrete Ports
- Message Signaled Interrupts (MSI)
- Access Control Service (ACS) Capability
- Capability only (no control functionality)
- Hot Plug support
- Static device number allocation
- Embedded Endpoint
- Up to 96 embedded endpoint devices (one embedded endpoint behind each switch downstream port)
- Up to 96 PFs maximum across all embedded endpoints
- Up to 2048 VFs across all embedded endpoints
- MSI/MSI-X interrupts
- Elastic PF configuration, which is the capability to update the configuration space at any time
- ACS Capability
- Capability only (no control functionality)
- Function Level Reset (FLR)
- Advanced Error Reporting (AER)
- Single Root I/O Virtualization (SR-IOV)
- Alternative Routing ID (ARI)
- VirtIO Capability
- Capability only
- No VirtIO PCI Configuration Access functionality
- Address Translation Service (ATS)
- TLP Processing Hints (TPH)
- IP
- Support for Agilex™ 7 FPGAs and SoCs and P-Tile based devices: Stratix® 10 DX FPGAs and SoCs
- Optimized gate count
- User packet interface with separate header, data and prefix
- User packet interface provides one TLP in any given cycle for all configurations
- Up to 512 outstanding Non-Posted requests (x16 core only)
- Up to 256 outstanding Non-Posted requests (x8 and x4 cores)
- Device-dependent PLD clock (coreclkout_hip) maximum frequency
- 500 MHz for Agilex™ 7 devices, 400 MHz for Stratix® 10 DX devices
Block Diagram
Technical Specifications
Related IPs
- Multichannel DMA Intel FPGA IP for PCI Express*
- Intel® FPGA IP for Ethernet Products Portfolio
- Intel® FPGA IP for PCIe
- Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core
- Intel® FPGA IP for DDR3 SDRAM High-Performance Controller
- Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)