Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high interface speeds intended for high performance computing. It is designed with a system-oriented approach to maximize flexibility and ease of integration for our customers.
The PMA ( Physical Media Attachment) is delivered as hard macro and the PCS ( Physical Coding sublayer ) as a synthesizable soft macro. The integrated PHY ( PCS+PMA) of PCIe Gen 5 is backward compatible to PCIe Gen 4/3/2/1/ and designed for various applications like chip_to_chip communication, SSD, HPC for enterprise solutions supporting upto 36dB channel loss. Our PHY architecture support wide range of links with our unique CMU (Clock Management Unit).
PHY IP provides high-performance low power architecture having multi-lane capability for the high-bandwidth applications. It meets the needs of today’s high speed chip-to-chip, board-to-board, and backplane interfaces while being low in power and area.
High Performance, Low Latency PCIe Gen5 PHY
Overview
Key Features
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
- Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- Continuous time linear equalizer (CTLE) with programmable settings
- Programmable/automatic calibration of key circuits
- Multi-lane support (x2,x4,x8,x16)
- Multi-tap Rx DFE (decision feedback equalizer)
- Programmable int./ext. loopback modes between TX and RX
- Low latency with fast symbol lock in CDR
- Common clock architecture SRNS/SRIS optional
- Includes ESD structures, Bump
- Operation across a wide temperature range(-40C to +125C)
- Supports upto 36dB channel loss
- Preventive measures for Burst errors in SerDes
- Eye monitoring and auto calibration
- Supports Industry standard third party controllers
Block Diagram
Applications
- High Performance Enterprise computing
- Storage (SSD NVMe) devices
- Automotive
- GPU interfacing
- Server connectivity
Deliverables
- GDS IILayouts
- LEF abstracts
- CDL netlists
- Liberty timings
- Verilog model with description
- A full datasheet
- An integration note
Technical Specifications
Short description
High Performance, Low Latency PCIe Gen5 PHY
Vendor
Vendor Name
Foundry, Node
TSMC 12nm FFC
TSMC
Silicon Proven:
28nm
HPC
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