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PCI Express PHY

Overview

PCIe is the most common protocol in high speed serial standards to connect components in embedded systems. It leverages SerDes (Serializer/De-serializer) technology to deliver throughput and latency performance greater than what is possible with wide parallel bus technology.

The vendor offers best-in-class PHY IP for PCIe 4.0/3.0/2.0. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) and soft macro for PCIe that is PIPE4.3 compliant.

Key Features

  • Quad PCIe 16/8/5/2.5 Gbps per lane
  • Tight control over termination resistor (~50 Ohm) with on chip calibration
  • Tight skew control of 1UI between lanes of the PMA
  • 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  • Lowest latency
  • Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
  • Programmable/automatic calibration of key circuits (pre-emphasis, eye-diagram monitoring / DFE tap calibration / offset calibration)
  • CDR logic for better data alignment and locking
  • Support for bifurcation and quadfurcation modes
  • 3-tap Rx DFE (decision feedback equalizer)
  • Programmable internal/external loopback modes between TX and RX
  • SRnS (Separate Reference no Spread) support
  • Includes ESD structures
  • Operation across a wide temperature range (-40 C to +125 C)

Deliverables

  • User and integration guides
  • Netlist
  • Timing library
  • Register map
  • Verilog
  • IBIS-AMI models
  • LEF views
  • Layout Versus Schematic (LVS)
  • Design Rule Check (DRC) reports
  • Silicon

Technical Specifications

Short description
PCI Express PHY
Vendor
Vendor Name
Foundry, Node
TSMC 12nm FFC
TSMC
Silicon Proven: 28nm HPC
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