A new era of chip-level DRC debug: Fast, scalable and AI-driven

By James Paris and Priyank Jain, Siemens EDA
EETimes | August 20, 2025

Physical verification has reached a turning point. As SoC designs explode in complexity, traditional debug methods are buckling under the weight of modern requirements. Parallel block development, rapid incremental signoff, and massive data volumes have pushed legacy tools far past their breaking point. Calibre Vision AI doesn’t just keep up—it redefines what’s possible, bringing lightning-fast, scalable DRC debug to the heart of tomorrow’s most ambitious chip projects. 

Why legacy DRC debug falls short at scale 

Physical implementation now unfolds in parallel. Blocks and partitions develop alongside the top-level design, and signoff happens at every stage. This accelerates growth, but it’s a recipe for complexity: advanced nodes unleash not thousands or millions, but billions of DRC violations. When every engineer is buried under cascading ASCII log files and endless manual filtering, finding the true root cause can take days of detective work—and the clock is always ticking. 

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