A new era of chip-level DRC debug: Fast, scalable and AI-driven
By James Paris and Priyank Jain, Siemens EDA
EETimes | August 20, 2025
Physical verification has reached a turning point. As SoC designs explode in complexity, traditional debug methods are buckling under the weight of modern requirements. Parallel block development, rapid incremental signoff, and massive data volumes have pushed legacy tools far past their breaking point. Calibre Vision AI doesn’t just keep up—it redefines what’s possible, bringing lightning-fast, scalable DRC debug to the heart of tomorrow’s most ambitious chip projects.
Why legacy DRC debug falls short at scale
Physical implementation now unfolds in parallel. Blocks and partitions develop alongside the top-level design, and signoff happens at every stage. This accelerates growth, but it’s a recipe for complexity: advanced nodes unleash not thousands or millions, but billions of DRC violations. When every engineer is buried under cascading ASCII log files and endless manual filtering, finding the true root cause can take days of detective work—and the clock is always ticking.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Articles
- DRC debugging challenges in AMS/custom designs at 20 nm
- Co-Design for SOCs -> On-chip support needed for SOC debug
- Co-Design for SOCs -> Designers face chip-level squeeze
- Co-Design for SOCs -> Software debug shifts to forefront of design cycle
Latest Articles
- FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant