IP Catalog > Security IP > Cryptography IP > Public Key Accelerator IP

Public Key Accelerator IP

Public key cryptography, or asymmetric cryptography, uses mathematical functions to create codes that are exceptionally difficult to crack, enabling designers to protect sensitive data and systems. Common public key algorithms include RSA, Digital Signature Algorithm (DSA), and Diffie-Hellman (DH), which require the calculation of complex modular exponentiation operations to encrypt, decrypt, sign, and verify data used in data encryption, digital signatures, and key exchanges. Similarly, the Elliptic Curve Cryptography (ECC) based algorithms require complex mathematical operations, such as point multiplications, and are designed to support devices with limited computing power or memory to encrypt internet traffic.

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Search (66)
Compare 66 Public Key Accelerator IP from 18 vendors (1 - 10)
  • Modular Exponentiation Core
    • Fully synthesisable RTL source code
    • VHDL/Verilog testbench with test vectors
    • User documentation
    Block Diagram -- Modular Exponentiation Core
  • Falcon IP Core
    • Falcon IP Core is a post-quantum digital signature algorithm (DSA).
    • It is currently under development. It is going to be compliant with Falcon specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    • Additionally, Falcon IP Core will be enhanced to achieve compliance with NIST Falcon Standart when it is released. 
    Block Diagram -- Falcon IP Core
  • Dilithium IP Core
    • Dilithium IP Core is a post-quantum digital signature algorithm (DSA).
    • It currently supports Sign and Verify functions, with key generation functionality planned for future implementation.
    • This IP is compliant with Dilithium specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    Block Diagram -- Dilithium IP Core
  • KYBER IP Core
    • supports encapsulation and decapsulation operations
    • supports all modes K=2,3,4.
    • is compliant with Kyber specification round 3.
    • has fully stallable input and output interfaces. 
    • Key generation feature is going to be implemented in the near future.
    Block Diagram -- KYBER IP Core
  • RSA Keygen IP Core
    • RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'.
    • This standard specifies methods for generating RSA key pairs.
    • RSA Keygen IP Cores support key pair generation up to 4096 bits.
    Block Diagram -- RSA Keygen IP Core
  • RSA IP Core
    • RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm specifications defined in 'FIPS 186'.
    • This standard specifies methods for digital signature generation and verification using the RSA Digital Signature Algorithm.
    • RSA IP cores support bit lengths from 256 to 4096.
    Block Diagram -- RSA IP Core
  • NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
    • Minimal Resource Requirements
    • Secure Architecture
    • FIPS 186-4 and SP 800-56A compliant
    Block Diagram -- NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
  • ECDSA IP Core
    • ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifications defined in 'FIPS 186'.
    • This standard specifies methods for digital signature generation and verification using the Elliptic Curve Digital Signature Algorithm (ECDSA). 
    Block Diagram -- ECDSA IP Core
  • Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
    • PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
    • With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
    Block Diagram -- Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
  • Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
    • The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
    Block Diagram -- Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
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