High-Performance SHA-2/HMAC Accelerator with Full SHA-2 Family Support and Low Latency SCA/FI Protection FortifyIQ’s SHA-2/HMAC I…
- SHA2 (SHA-256)
Cryptography IP cores provide hardware-based security functions for protecting data, communications, and digital assets in modern SoC and ASIC designs. By offloading cryptographic operations from software, these IP cores deliver higher performance, lower latency, improved energy efficiency, and stronger resistance to security attacks.
This category includes Symmetric Cryptography, Public Key Cryptography, Post-Quantum Cryptography (PQC), Hash / MAC, and Random Number Generator (RNG) IP solutions. Available implementations may support algorithms such as AES, ChaCha20, RSA, ECC, ML-KEM, ML-DSA, SHA-2, SHA-3, HMAC, CMAC, and true or deterministic random number generation technologies required for secure key management and authentication.
This catalog enables semiconductor engineers to evaluate and compare Cryptography IP from leading vendors based on supported algorithms, security certifications, throughput, latency, power consumption, silicon area, side-channel resistance, quantum-safe capabilities, and semiconductor process node compatibility.
High-Performance SHA-2/HMAC Accelerator with Full SHA-2 Family Support and Low Latency SCA/FI Protection FortifyIQ’s SHA-2/HMAC I…
HMAC-SHA256 Secure Core - Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection FortifyIQ’s SHA-2/HMAC IP core delivers high-speed, ha…
High-Performance AES Encryption Core with GCM/XTS Support and SCA/FI Protection FortifyIQ’s High-Performance AES Encryption Core …
ML-KEM / ML-DSA Post-Quantum Cryptography IP
ML-KEM (Crystals-Kyber) and ML-DSA (Crystals-Dilithium) are Post-Quantum Cryptographic (PQC) algorithms, meaning they are mathema…
SHA256 is a Secure Hash Algorithms which is one of the latest hash functions standarized by the U.S Federal Government.
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSC…
SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010,…
CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Encryption Standard.
HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
This is a high performance, small footprint HASH IP Core.
AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
This is a high performance, small footprint crypt/decrypt IP Core.
The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of Chi…
The AES-XTS Multibooster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suit…
Advanced Encryption Standard Cryptographic Co-Processor
The DAES IP Core is a high-performance AES hardware accelerator designed to execute Encryption Standard (AES) operations with exc…
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACse…
The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224.
The eSi-SHA1 core is an easy to use SHA1 hash accelerator peripheral.
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC753…
True Random Number Generator (TRNG)
1.5Tb MACsec ENGINE True Random Number Generators (TRNGs) are used to generate statistically independent streams of bits for vari…
The security strength of many systems and applications is dependent on the quality of random number generators.
SHA IP Core with native SHA2-256 HMAC support
The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4.