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Hash and HMAC Accelerator IP

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Compare 83 Hash and HMAC Accelerator IP from 34 vendors (1 - 10)
  • SHA-256 IP
    • SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles.
    • Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. 
    Block Diagram -- SHA-256 IP
  • SHA512 & SHA384 core
    • Simple register based interface
    • 81 clock cycles per 1024 bits of input data
    • AMBA 3 APB slave interface
    • DMA flow-control interface
    Block Diagram -- SHA512 & SHA384 core
  • SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
    • Supports variable length SHA-3 Hash Functions
    • Supports Extendable Output Functions (XOF)
    • Configurable architecture for achieving the required performance and silicon area
    Block Diagram -- SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
  • SHA256 & SHA224 core
    • Simple register based interface
    • 65 clock cycles per 512 bits of input data
    • AMBA 3 APB slave interface
    • DMA flow-control interface
    Block Diagram -- SHA256 & SHA224 core
  • SHA1 core
    • Simple register based interface
    • 82 clock cycles per 512 bits of input data
    • AMBA 3 APB slave interface
    • DMA flow-control interface
    Block Diagram -- SHA1 core
  • SHA-256 Secure Hash Function
    • Compliant to FIPS 180-2 specification of SHA-256.
    • Bit padding internally implemented.
    • Supports 2^64-1 bits maximum message length.
    • Supports input message length multiple of 8-bit.
    • Initial value of the chaining variables selected before synthesis.
    Block Diagram -- SHA-256 Secure Hash Function
  • SHA-1 Secure Hash Function
    • Compliant to FIPS 180-1 specification of SHA-1.
    • Bit padding internally implemented.
    • Supports 2^64-1 bits maximum message length.
    • Supports input message length multiple of 8-bit.
    Block Diagram -- SHA-1 Secure Hash Function
  • MD5 IP Core Message Digest Function
    • The MD5 IP core is a high-performance implementation of the MD5 Message-Digest algorithm, a one-way hash function, compliant to the RFC 1321 specification.
    • The core is composed of two main units, the MD5 Engine and the Padding Unit.
    • The MD5 Engine applies the MD5 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last message block.
    Block Diagram -- MD5 IP Core Message Digest Function
  • Poly1305 Crypto Accelerator
    • Wide bus interface (128-bit data, 128-bit keys, 135-bit digest) or 32-bit register interface
    • Key size: 128 bits
    • Includes initialization stage
    • Supports continuation mode
    • Fully synchronous design
    Block Diagram -- Poly1305 Crypto Accelerator
  • SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators
    • HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SHA-3 (FIPS-202), up to 8 Gbps.
    • Designed for fast integration, low gate count and full transforms, the HMAC-IP-59 accelerators provide a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
    Block Diagram -- SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators
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Semiconductor IP