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Hash and HMAC Accelerator IP

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Compare 79 Hash and HMAC Accelerator IP from 36 vendors (1 - 10)
  • SHA1, SHA2 Cryptographic Hash Cores
    • Completely self-contained; does not require external memory
    • SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2.
    • HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input.
    • Flow-through design; flexible data bus width
    Block Diagram -- SHA1, SHA2 Cryptographic Hash Cores
  • Secure Hash Algorithm 512 IP Core
    • FIPS PUB 180-4 compliant SHA2-512 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224, 256, 384, 512-bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 512 IP Core
  • Secure Hash Algorithm 384 IP Core
    • FIPS PUB 180-4 compliant SHA2-384 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224, 256, 384-bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 384 IP Core
  • Secure Hash Algorithm 256 IP Core
    • FIPS PUB 180-4 compliant SHA2-256 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224 and 256 bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 256 IP Core
  • SHA-1 Processor
    • Suitable for data authentication applications.
    • Fully synchronous design.
    • Available as fully functional and synthesizable VHDL or Verilog soft-core.
    • Xilinx and Altera netlist available for various devices.
    Block Diagram -- SHA-1 Processor
  • MD5 Processor
    • RFC 1321 compliant.
    • Suitable for data authentication applications.
    • Fully synchronous design.
    • Available as fully functional and synthesizable VHDL or Verilog soft-core.
    Block Diagram -- MD5 Processor
  • SHA-256 Processor
    • This core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
    • The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.
    Block Diagram -- SHA-256 Processor
  • Block Diagram -- Fast Hash IP core
  • Tiny Hash IP core
    • The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate applications.
    • The core is available in versions which support any combination of the secure hashing algorithms described in the Secure Hash Standard, FIPS PUB 180-3; namely SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512.
    • It can also support the standard Hash-based Message Authentication Code (HMAC) algorithm described in FIPS PUB 198-1 which is widely used for data authentication and integrity checking in a number of common data security protocols.
    Block Diagram -- Tiny Hash IP core
  • SHA3 IP Core
    • SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard specifies methods for generating secure hash values using the SHA-3 algorithm. 
    • SHA3 IP Cores support the SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256 functions, and are byte-oriented in their implementation.
    Block Diagram -- SHA3 IP Core
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