UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation
A self-driving car. A helicopter drone on Mars. A thermostat you can adjust from across the globe. What’ll they think of next? Science fiction writer and futurist, Arthur C. Clark, said that “any sufficiently advanced technology is indistinguishable from magic.” The thing is, it’s not magic. It’s engineering. And there are a lot of challenges to work through to make the proverbial “magic” happen. One of the biggest challenges is the continually encroaching power-performance-and-area (PPA) ceiling in traditional monolithic SoC design. To achieve the next big phase of innovation and break the PPA ceiling, you must design differently. And one trend to help you do just that is multi-die chip design.
A multi-die design consists of individual dies, also called chiplets, that support discrete functions and are assembled together—either side-by-side on 2D or 2.5D packages or vertically stacked in 3D packages. The chiplets could be manufactured on different process nodes in a heterogeneous fashion. Until now, employing a multi-die architecture has been difficult. To do it, early adopters have adapted monolithic chip design methodologies to internally defined design and verification flows and developed their own interface technologies. But to make the marketplace for disaggregated dies truly vibrant—one with plug-and-play-like flexibility and interoperability—industry standards and an ecosystem are essential. Enter the Universal Chiplet Interconnect Express (UCIe) specification that enables customizable, package-level integration of chiplets.
To read the full article, click here
Related Semiconductor IP
- The UCIe CONTROLLER IP
- UCIe D2D Adapter
- Simulation VIP for UCIE
- UCIe Verification IP
- UCIe 2.0 Verification IP
Related Blogs
- UCIe: Enabling the Chiplet-Based Ecosystem
- Arm Ecosystem Collaborates on Standards to Enable a Thriving Chiplet Market
- Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
- Jumpstarting the Automotive Chiplet Ecosystem
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms