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UCIe IP

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Search (54)
Compare 54 IP from 15 vendors (1 - 10)
  • UCIe Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe Verification IP
  • UCIe 2.0 Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe 2.0 Verification IP
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe Controller baseline for Streaming Protocols
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
    • Error detection and correction with optional CRC and retry functionality
    Block Diagram -- UCIe Controller baseline for Streaming Protocols
  • UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 48-Gsps peak sample rate
    • 8 bit resolution
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 12-Gsps peak sample rate
    • 12 bit resolution (programmable)
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • D2D UCIe 1.0
    • Compatible with UCIe v1.0 specification
    • Single-ended, source synchronous and DDR IO Signaling
    • Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
    • High clock frequency, up to 8GHz
    Block Diagram -- D2D UCIe 1.0
  • UCIe IP Solutions
    • Low Latency controller for UCIe-based die-to-die connectivity
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports streaming, CXL and PCI Express protocols
    • Error detection and correction with optional CRC and retry functionality
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
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