UCIe IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 76 IP from 24 vendors (1 - 10)
  • UCIe TX Interface
    • Transmit-only UCIe REV1.1 with FIFO Interface
    • TSMC 16FFC process
    • Low power UCIe D2D
    • 1 pJ/bit at 0.7V
    Block Diagram -- UCIe TX Interface
  • UCIe RX Interface
    • Receive-only UCIe Rev1.1 with FIFO Interface
    • Samsung 8nm process
    • Low power UCIe D2D
    • 1 pJ/bit at 0.7V
    Block Diagram -- UCIe RX Interface
  • AXI-S Protocol Layer for UCIe
    • Configurable Data width
    • AXI4 Stream and AXI5 Stream Compliant
    • All handshaking features including wakeup
    • strb and keep for data flagging
    Block Diagram -- AXI-S Protocol Layer for UCIe
  • UCIe IP
    • Supporting x16 link width with speeds up to 16 GT/s per lane, it conforms to UCIe’s standardized interface for seamless chiplet integration.
    • Developed on GlobalFoundries 12LP+, this IP includes custom PHY, protocol, and die-to-die layers—engineered for performance, flexibility, and low latency.
  • UCIe PHY (Die-to-Die) IP
    • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
    • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
    • Provides a 1024-bit data bus width with high-throughput die-to-die communication
    • Includes automatic per-lane calibration and optional transmitter de-emphasis
    Block Diagram -- UCIe PHY (Die-to-Die) IP
  • UCIe Controller add-on CXL2 Protocol Layer

     

    • UCIe Controller add-on CXL2 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL2 Protocol Layer
  • UCIe Controller add-on CXL3 Protocol Layer
    • UCIe Controller add-on CXL3 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL3 Protocol Layer
  • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    Block Diagram -- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
  • Verification IP for UCIe
    • Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics.
    • PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.
    Block Diagram -- Verification IP for UCIe
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
×
Semiconductor IP