Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
Cadence demonstrated multiple IP for die-to-die connectivity at Chiplet Summit 2024. Conference attendees discussed their chiplet and multi-die design needs with our experts and learned how Cadence’s IP can support them in achieving their system needs with optimum PPA targets. Our UCIeTM IP silicon demo created a buzz with its extensive testing.
Cadence unveiled the first silicon of its UCIe IP with organic package at the summit. In an industry first, Cadence proved successful bring-up and data traffic across the complete range of interconnect distances—short-, medium-, and long-reach channels—operating at 16GT/s speeds with wide open data eyes. The stringent UCIe requirements must be met across all interconnect distances per the standard requirements. Cadence was the only IP provider that demonstrated successful 5mm, 15mm, and 25mm long-reach UCIe operation at the summit, setting the gold standard with its thorough measurement and reporting.
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Related Semiconductor IP
- UCIe D2D Adapter
- UCIe Die-to-Die Chiplet Controller
- Verification IP for UCIe
- UCIe Die-to-Die Controller IP
- UCIe Die-to-Die PHY
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