On-chip interfaces gain importance in next-gen FPGAs
August 12, 2013
Maybe it was mere coincidence that Altera Corp announced new work with Cavium on multiprocessing, just as the MemCon memory bus conference opened in Santa Clara. Maybe the new IP core pacts announced by Cadence, Synopsys, and Lattice were a tangential sideshow to MemCon. Or maybe there is a common realization that the future belongs to successful synthesizable implementations of DDR3, RDRAM, Interlaken, and other high-speed interfaces that operate intra-chip and inter-chip.
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