On-chip interfaces gain importance in next-gen FPGAs
August 12, 2013
Maybe it was mere coincidence that Altera Corp announced new work with Cavium on multiprocessing, just as the MemCon memory bus conference opened in Santa Clara. Maybe the new IP core pacts announced by Cadence, Synopsys, and Lattice were a tangential sideshow to MemCon. Or maybe there is a common realization that the future belongs to successful synthesizable implementations of DDR3, RDRAM, Interlaken, and other high-speed interfaces that operate intra-chip and inter-chip.
To read the full article, click here
Related Semiconductor IP
- Interlaken Verification IP
- Interlaken Look-Aside Intel® FPGA IP
- Interlaken Intel® FPGA IP
- Interlaken Controller
- Interlaken Verification IP
Related Blogs
- The interface makes the FPGA
- SSD Interfaces and Performance Effects
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
Latest Blogs
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Keeping Pace with CXL Specification Revisions
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring