On-chip interfaces gain importance in next-gen FPGAs
Maybe it was mere coincidence that Altera Corp announced new work with Cavium on multiprocessing, just as the MemCon memory bus conference opened in Santa Clara. Maybe the new IP core pacts announced by Cadence, Synopsys, and Lattice were a tangential sideshow to MemCon. Or maybe there is a common realization that the future belongs to successful synthesizable implementations of DDR3, RDRAM, Interlaken, and other high-speed interfaces that operate intra-chip and inter-chip.
To read the full article, click here
Related Semiconductor IP
- Interlaken Verification IP
- Interlaken Synthesizable Transactor
- INTERLAKEN IIP
- Interlaken Verification IP
- Interlaken Controller
Related Blogs
- Open ARM-wrestling in FPGAs
- Why FPGA startups keep failing
- Over-interpreting the extended ARM
- Lattice sticks with open RISC
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms