On-chip interfaces gain importance in next-gen FPGAs
August 12, 2013
Maybe it was mere coincidence that Altera Corp announced new work with Cavium on multiprocessing, just as the MemCon memory bus conference opened in Santa Clara. Maybe the new IP core pacts announced by Cadence, Synopsys, and Lattice were a tangential sideshow to MemCon. Or maybe there is a common realization that the future belongs to successful synthesizable implementations of DDR3, RDRAM, Interlaken, and other high-speed interfaces that operate intra-chip and inter-chip.
To read the full article, click here
Related Semiconductor IP
- Interlaken Controller
- Interlaken IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Interlaken Core (Up to 600G)
- UltraScale / UltraScale+ Interlaken
Related Blogs
- Open ARM-wrestling in FPGAs
- Why FPGA startups keep failing
- Over-interpreting the extended ARM
- Lattice sticks with open RISC
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview