The INTERLAKEN Verification IP Product is the comprehensive INTERLAKEN interface protocol validation solution. INTER LAKEN interface is widely used in networking based SoCs as scalable packet interface for packet transfer. INTERLAKEN VIP inte grates automatic constrain random stimulus generation, assertion, protocol checking and functional coverage within a single extensible component, which incorporates INTERLAKEN protocol operation with full duplex packet transfer for channels that significantly re duces the time and cost of verifying complex INTERLAKEN based target system designs.
INTERLAKEN VIP provides a simple yet pow erful user interface which drastically reduces the time and effort needed to create a verifi cation environment and verify thoroughly to ensure first time right silicon. User can verify the complex design with few test cases in very short time instead of running multiple directed test cases.
INTERLAKEN VIP is reusable, highly configu rable, pre-verified, plug-and-play verification component developed in System Verilog - UVM, which is solution for networking based SoC incorporating INTERLAKEN packet interface protocol at Module, Chip and System level.
INTERLAKEN VIP is developed using System Verilog, the unified language for Design & Verification and UVM reusable verification methodology.
INTERLAKEN VIP comprises of following major elements.
- Bus Function Model [BFM]
- Monitor
- Generator : Sequences & Sequencer
- Protocol Checkers
- APIs
- Callbacks
- Coverage Capability
- Assertions
- Configuration
- Report Generator
INTERLAKEN VIP comprises of following major elements:
| Bus Function Model [BFM] | Monitor |
| Generator: Sequences & Sequencer | Protocol Checkers |
| APIs | Callbacks |
| Coverage Capability | Assertions |
| Configuration | Report Generator |
