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Interlaken IP

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  • Interlaken Controller
    • MAC layer with fast AMBA CXS interface
    • PCS layer highly configurable
    • 64B/67B encoding/decoding supported
    Block Diagram -- Interlaken Controller
  • Interlaken Communication Controller
    • Up to 8 lanes and each lane operating at data rates up to 6.25 Gbs
    • Link resiliency with support for operation with fewer lanes
    • Support for up to 256 channels
    • Implements out-of-band and in-band flow control
    Block Diagram -- Interlaken Communication Controller
  • Interlaken IP
    • Compliant with Interlaken protocol specification v1.2
    • Interlaken look as side protocol 1.1
    • Interlaken retransmission extension specification 1.2
    • Interlaken Reed-Solomon Forward Error Correction Extension 1.1
  • Interlaken Core (Up to 600G)
    • Support for up to 600 Gbps of throughput
    • Data striping and de-striping across 1 to 24 lanes
    • Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
    • Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
  • UltraScale / UltraScale+ Interlaken
    • The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
    • The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
    • The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
  • UltraScale Interlaken
    • The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
    • The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
    • The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
  • Interlaken, 40G, 8 Lanes
    • Local serial loop-back from transmitter to receiver at serial transceiver for self test
  • Interlaken, 150G, 24 Lanes
    • Receiver-link fault status detection
  • Interlaken, 100G, 20 Lanes
    • Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
  • Interlaken, 50G for 28nm devices
    • High-performance internal system interfaces
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