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Interlaken IP

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Compare 26 IP from 9 vendors (1 - 10)
  • Interlaken Verification IP
    • Implemented natively in OpenVera, Verilog, SystemC, Specman E and SystemVerilog.
    • Follows Interlaken specification as defined in Interlaken protocol definition v1.2.
    • Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
    • Compliant to Interlaken protocol specification v1.2
    Block Diagram -- Interlaken Verification IP
  • Interlaken Synthesizable Transactor
    • Follows Interlaken specification as defined in Interlaken protocol definition v1.2
    • Supports Interlaken look aside protocol specification v1.0
    • Supports Interlaken retransmission extension specification 1.1
    • Supports multi-channel implementation as per the specification
    Block Diagram -- Interlaken Synthesizable Transactor
  • INTERLAKEN IIP
    • Compliant with Interlaken protocol specification v1.2
    • Interlaken look as side protocol 1.1
    • Interlaken retransmission extension specification 1.2
    • Interlaken Reed-Solomon Forward Error Correction Extension 1.1
    Block Diagram -- INTERLAKEN IIP
  • Interlaken Verification IP
    • Compliant to Interlaken Protocol Specification Rev 1.2, Interlaken Look-Aside Protocol Definition Rev 1.1, Interlaken Retransmit Extension Protocol Definition Rev 1.2, Interlaken Interoperability Recommendation v 1.9.
    • Complainto theReed Solomon Forward Error Correction Extension 1.0
    • Configurable BurstMax, BurstMin, BurstShort size, Meta Frame Length, Channel ON/OFF.
    • Configurable Number of lanes. Up to 64K channels using Multi-Use bits.
    Block Diagram -- Interlaken Verification IP
  • Interlaken Controller
    • MAC layer with fast AMBA CXS interface
    • PCS layer highly configurable with up to 48 lanes
    • Multi-lane configurations, up to 48 lanes
    • 64B 67B encoding/decoding supported
    Block Diagram -- Interlaken Controller
  • Interlaken Core (Up to 600G)
    • Support for up to 600 Gbps of throughput
    • Data striping and de-striping across 1 to 24 lanes
    • Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
    • Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
  • UltraScale / UltraScale+ Interlaken
    • The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
    • The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
    • The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
  • UltraScale Interlaken
    • The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
    • The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
    • The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
  • Interlaken, 40G, 8 Lanes
    • Local serial loop-back from transmitter to receiver at serial transceiver for self test
  • Interlaken, 150G, 24 Lanes
    • Receiver-link fault status detection
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