The interface makes the FPGA
November 26, 2009
Announcements from the FPGA industry this week continue the trend of the past year of placing the serial interface before the gate count or the core-logic IP – an understandable strategy, given the number of vertical markets for which interface virtually defines application (note that I did not say raw speed, though that is a secondary consideration).
Related Semiconductor IP
- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
- I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
- I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
Related Blogs
- On-chip interfaces gain importance in next-gen FPGAs
- Open ARM-wrestling in FPGAs
- Why FPGA startups keep failing
- Over-interpreting the extended ARM