The interface makes the FPGA
November 26, 2009
Announcements from the FPGA industry this week continue the trend of the past year of placing the serial interface before the gate count or the core-logic IP – an understandable strategy, given the number of vertical markets for which interface virtually defines application (note that I did not say raw speed, though that is a secondary consideration).
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- UA Link DL IP core
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- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
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