The interface makes the FPGA
Announcements from the FPGA industry this week continue the trend of the past year of placing the serial interface before the gate count or the core-logic IP – an understandable strategy, given the number of vertical markets for which interface virtually defines application (note that I did not say raw speed, though that is a secondary consideration).
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- On-chip interfaces gain importance in next-gen FPGAs
- Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing
