Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon 24
PCI-SIG DevCon 2024 – 32nd Anniversary
For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.
Why Are Standards Like PCIe So Important?
From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.
HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.
Related Semiconductor IP
- PCIe 7.0 PHY in TSMC (N5, N3P)
- PCIe 7.0 Switch
- PCIe 7.0 Retimer Controller
- PCIe 7.0 Controller with AXI
- PCIe 7.0 Controller
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- Industry's First Adopted VIP for PCIe 7.0
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- Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Technique
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