PCIe 7.0 Retimer Controller
Overview
The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market for PCIe 7.0 retimer chips.
Key Features
- Supports PCIe 7.0 128 GT/s speeds at up to x16 lanes
- CXL 3.0 aware
- Supports PIPE 6.2.1 compatible PHYs
- Optimized for low latency
- Highly-configurable equalization algorithms and adaptive behaviors
- Pre-integrated XpressAGENT™ debug monitor
- Supports up to 4 retimers in series per the retimer protocol specification
Deliverables
- IP Files
- Verilog RTL source code
- IPXACT files for registers
- Software API in C and Python for XpressAGENT (debug monitor)
- Documentation
- Retimer IP User Guide
- Getting Started Guide
- Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project and DC constraint files (ASIC)
- Lint and CDC scripts
Technical Specifications
Foundry, Node
Any