Industry's First Adopted VIP for PCIe 7.0
PCIe technology has evolved over three decades, marking its 30th anniversary with the unveiling of PCIe 7.0. This latest standard doubles IO bandwidth to 128GT/s, emphasizing low latency and high reliability while maintaining compatibility with previous generations. Key features on the physical layer include the adoption of PAM4 signaling, 1b/1b encoding, and a robust Forward Error Correction (FEC) mechanism same as PCIe 6.0.
Industry Adoption Trends
PCIe 7.0 is set to see rapid adoption, driven by its streamlined transition from PCIe 6.0. The market has already witnessed the release of PCIe 7.0 SerDes test chips and testing equipment following the introduction of PCIe 7.0 rev0.5 in February 2024. With PCIe 7.0 rev1.0 expected to be finalized by mid-2025, the standard is poised to meet the escalating bandwidth needs of AI/ML, Cloud, HPC, and other demanding applications.
To read the full article, click here
Related Semiconductor IP
- MIPI SoundWire I3S Peripheral IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
Related Blogs
- Industry's First Verification IP for PCIe 7.0
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- PCIe Spread Spectrum Clocking (SSC) for Verification Engineers
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained