Industry's First Adopted VIP for PCIe 7.0
PCIe technology has evolved over three decades, marking its 30th anniversary with the unveiling of PCIe 7.0. This latest standard doubles IO bandwidth to 128GT/s, emphasizing low latency and high reliability while maintaining compatibility with previous generations. Key features on the physical layer include the adoption of PAM4 signaling, 1b/1b encoding, and a robust Forward Error Correction (FEC) mechanism same as PCIe 6.0.
Industry Adoption Trends
PCIe 7.0 is set to see rapid adoption, driven by its streamlined transition from PCIe 6.0. The market has already witnessed the release of PCIe 7.0 SerDes test chips and testing equipment following the introduction of PCIe 7.0 rev0.5 in February 2024. With PCIe 7.0 rev1.0 expected to be finalized by mid-2025, the standard is poised to meet the escalating bandwidth needs of AI/ML, Cloud, HPC, and other demanding applications.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- Industry's First Verification IP for PCIe 7.0
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- PCIe Spread Spectrum Clocking (SSC) for Verification Engineers
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview