Massively parallel frameworks for in-design verification
David White & Xiao Lin, Cadence
EDN (October 24, 2016)
In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. This article explores how these massively parallel frameworks can be combined with in-design verification methodologies to allow field solvers to provide golden levels of extraction and simulation accuracy at acceptable levels of performance for larger designs.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)
- Implementing Parallel Processing and Fine Control in Design Verification
- Early Interactive Short Isolation for Faster SoC Verification
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks