Massively parallel frameworks for in-design verification
David White & Xiao Lin, Cadence
EDN (October 24, 2016)
In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. This article explores how these massively parallel frameworks can be combined with in-design verification methodologies to allow field solvers to provide golden levels of extraction and simulation accuracy at acceptable levels of performance for larger designs.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)
- Implementing Parallel Processing and Fine Control in Design Verification
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- Design-Stage Analysis, Verification, and Optimization for Every Designer
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems