Massively parallel frameworks for in-design verification
David White & Xiao Lin, Cadence
EDN (October 24, 2016)
In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. This article explores how these massively parallel frameworks can be combined with in-design verification methodologies to allow field solvers to provide golden levels of extraction and simulation accuracy at acceptable levels of performance for larger designs.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)
- Implementing Parallel Processing and Fine Control in Design Verification
- Early Interactive Short Isolation for Faster SoC Verification
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
Latest Articles
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation