Massively parallel frameworks for in-design verification
David White & Xiao Lin, Cadence
EDN (October 24, 2016)
In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. This article explores how these massively parallel frameworks can be combined with in-design verification methodologies to allow field solvers to provide golden levels of extraction and simulation accuracy at acceptable levels of performance for larger designs.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)
- Implementing Parallel Processing and Fine Control in Design Verification
- A closer look at security verification for RISC-V processors
- A formal-based approach for efficient RISC-V processor verification
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions