Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)
March 18, 2008 -- pldesignline.com
Multi-mode sensor processing – such as that for radar beamforming and for electro- optical (E-O) or infrared (IR) image processing – presents formidable computing problems. It requires extremely high data throughput and processing power, which requirements change dynamically with operating conditions.
Multi-mode sensor processing has traditionally been implemented using DSPs or FPGAs, but their lack of run-time programmability and re-configurability forces the worst-case design for each type of device. This creates a tremendous need for a solution that is upwardly scalable, reconfigurable, and programmable, all while reducing development costs and time to market.
The Massively Parallel Processor Array (MPPA) solution
Ambric (www.ambric.com) has developed a new computing architecture and device – a Massively Parallel Processor Array (MPPA) – that can be reconfigured in real time to adapt on-demand to the dynamic computational and functional requirements of multi-mode sensor platforms.
Performance of up to one TeraOPS
The ultra-high-performance Ambric Am2045 MPPA features 336 32-bit RISC processors delivering up to one teraOPS processing speed. It also features programmable 32-bit communication fabric for high-performance inter-processor connections. The Am2045 also includes a four-lane PCI Express interface and four GPIO ports, with an aggregate I/O bandwidth of 29 Gbps per second.
Scalability with no need to change design methodology
The Ambric Am2045 MPAA may be scaled to application requirements simply by reallocating computing resources (processors and/or memories) available within the chip or across multiple chips. The Ambric Structural Object Programming Model enables applications to add or reconfigure resources with no major design overhaul. This keeps development on schedule.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- Massively parallel frameworks for in-design verification
- SoC Test and Verification -> Assertions speed processor core verification
- High-Performance DSPs -> Processor boards: Architecture drives performance
- Network processor designer tackles verification 'nightmare'
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS