FlexGen Streamlines NoC Design as AI Demands Grow
By Abhishek Jadhav, embedded.com
As semiconductor designs evolve in complexity and scale, the role of interconnect IP becomes increasingly central to performance, power efficiency, and time to market. To address this, Arteris has introduced FlexGen, an AI-augmented network-on-chip (NoC) interconnect IP platform aimed at simplifying and accelerating the design process for system-on-chip (SoC) and chiplet-based architectures.
FlexGen builds on Arteris’s FlexNoC 5 technology and leverages a large library of system IP to automate NoC generation. It is designed to support a broad spectrum of processor architectures, including Arm, RISC-V, and x86. FlexGen integrates machine learning and physical design awareness to optimize topologies based on a user’s performance goals and floor-planning constraints.
To read the full article, click here
Related Semiconductor IP
- Smart Network-on-Chip (NoC) IP
- FlexNoC 5 Interconnect IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- Network-on-Chip (NoC)
- NoC Verification IP
Related News
- Arteris Revolutionizes Semiconductor Design with FlexGen – Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- Arteris To Provide FlexGen Smart NoC IP In Next-Generation AMD AI Chiplet Designs
- SoCs Get a Helping Hand from AI Platform FlexGen
- Automating NoC Design Masters SoC Complexity
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data