For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels.
Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.
FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
Overview
Key Features
- Data protection through ECC and parity checking
- Out-of-the-box support for ARM Cortex-R Processors
- Port Checking
- Unit protection by duplication and redundancy
- Similar to dual-core lockstep (DCLS) and often required for ASIL C or D systems as specified in the automotive ISO 26262 standard
- Duplicate unit checkers and fault safety controller
- Built in Self-Test (BIST) for resilience functions
- Data protection by monitoring
- Data packet integrity checkers
- Easy partitioning of any SoC into resilient and non-resilient domains.
Block Diagram
Technical Specifications
Maturity
In production chips
Availability
now
Related IPs
- ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive SoC development and accelerate ISO 26262 qualification
- 32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- FlexNoC 5 Option For Scalability and Performance Critical Systems
- Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder