Dolphin Integration releases its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density
March 30, 2007
-- Dolphin Integration, the Enabler of mixed signal SoCs, has released its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density.
Saving both ultra-low dynamic power and leakage, while maintaining an extremely high density, is a dream of every SoC integrator. With the announcement of its upcoming product, spRAM uLCeHD: URANUS 90LP/GP this Provider is on its way towards fulfilling this paradoxical dream.
It enables traveling with portable devices which demands these three important characteristics. The product is released at once in LP as well as in GP process and available on request at half nodes.
For more information, please visit:
http://www.dolphin.fr/flip/ragtime/90/ragtime_90_ram.html
Related Semiconductor IP
- TSN Ethernet Endpoint Controller 10Gbps
- 13ns High-Speed Comparator with no Hysteresis
- Frequency Divider
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
Related News
- Ultra high density standard cell library SESAME uHD-BTF to enrich Dolphin Integration's panoply at TSMC 90 nm eF and uLL
- Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm
- Dolphin Integration unveils a new RAM dedicated to IoT and Low Power MCU applications in 55 nm, GLOBALFOUNDRIES LPx process
- Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm
Latest News
- Accellera Approves Clock and Reset Domain Crossing (CDC/RDC) Standard 1.0 for Release
- Jmem Tek Joins the Intel Foundry Accelerator Ecosystem Alliance Program, Enabling JPUF and Post-Quantum Security Designs
- Credo Acquires CoMira Solutions
- Nvidia Sells Arm Shares, Signals Realignment of AI Portfolio
- Innatera Selects Synopsys Simulation to Scale Brain-Inspired Processors for Edge Devices