Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm
Grenoble, France - June 23, 2016 -- Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in.
Designers of low-power SoCs targeting 55 nm are proposed two self-contained kits, of Silicon IPs, with design methodologies, at a very attractive price up until the Green Thursday, June 30. Each kit is tailored to a major SoC challenge:
- For SoCs mostly in sleep mode: Power Regulation & Control Network kit
- For high duty-cycle SoCs: Voltage Regulation Network kit
REQUEST A “GREEN THURSDAY” QUOTE VALID UNTIL JUNE 30,2016
Such kits may be complemented with Foundation, Fabric and Feature IPs – such as standard cell libraries, memory generators, WhisperTrigger voice activity detector, uLP oscillators… – to combine the best power consumption, whatever the mode of activity of the SoC, with the smallest silicon area.
A catalog providing an overview of this consistent offering of Silicon IPs in 55 nm is immediately available on request.
About Dolphin Integration
DOLPHIN Integration contributes to "enabling low-power Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at low-power consumption.
"Foundation IPs" includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. "Fabric IPs" of voltage regulators, Power Island Construction Kit and their control network MAESTRO enable to safely implement low-power SoCs with the smallest silicon area. They also star the "Feature IP": from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.
Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make DOLPHIN Integration a genuine one-stop shop addressing all customers' needs for specific requests.
It is not just one more supplier of Technology, but the provider of the DOLPHIN Integration know-how!
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related News
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
- Dolphin Integration reveals its unique Regulator offering for IoT markets at 55 nm
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- Dolphin Integration introduces a new generation of SpRAM at 55 nm
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing