The SM4-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the SM4 algorithm (a block cipher specifi…
- SM4
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
The SM4-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the SM4 algorithm (a block cipher specifi…
Hardware root key generation and storage that never leaves the chip PUFrt includes a 1024-bit physical unclonable function (PUF) …
Deterministic Random Bit Generator (DRBG)
The Deterministic Random Bit Generator is an essential silicon-proven digital IP core for all FPGA, ASIC and SoC designs that tar…
100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
CryptOne is a fully scalable, hardware-accelerated cryptographic system built on 20+ years of DCD-SEMI’s engineering experience.
The IPsec Engine implements RFC4301 and other relevant RFCs, providing confidentiality, connectionless data integrity, data-origi…
Chacha20-Poly1305 Multi-Booster
The ChaCha20-Poly1305 Multi-Booster Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (…
The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standa…
The Securyzr™ MACsec Engine, also known as Media Access Control Security, implements the latest IEEE 802.1AE specification, provi…
The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash.
Anti-Counterfeiting Digital IP - Self-aware and Anti-bypass
Protection of the embedded secrets against professional hackers stealing actions Protection of Non-Volatile-Memory to make sure t…
The SNOW3G IP core is 3GPP confidentiality and integrity algorithms (UEA2/UIA2) stream cipher for telecommunication applications,…
The KASUMI IP core is 3GPP confidentiality and integrity algorithms (UEA1/UIA1) stream cipher for telecommunication applications,…
The ZUC IP core is 3GPP confidentiality and integrity algorithms (EEA3/EIA3) stream cipher for telecommunication applications, re…
The SHA-3 crypto engine has integrated flexibility and scalability to allow for high throughput and a configurable number of hash…
Small RSA/ECC Public Key Accelerators
The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate …
Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
The Protocol-IP-197 Multi-Protocol Engine is an IP family for accelerating IPSec, SSL, TLS, DTLS (CAPWAP), 3GPP and MACsec up to …
The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function…
Multi-Protocol Engine, Look-Aside, 1 Gbps
The Protocol-IP-93 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, and SRTP up to 1 Gbps…
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1.
The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification.