CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Encryption Standard.
- AES
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Encryption Standard.
XIP7131C is a compact 1 Intellectual Property (IP) core for TLS 1.3 client-side functionality.
HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
This is a high performance, small footprint HASH IP Core.
AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
This is a high performance, small footprint crypt/decrypt IP Core.
The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of Chi…
The AES-XTS Multibooster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suit…
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACse…
The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224.
The eSi-SHA1 core is an easy to use SHA1 hash accelerator peripheral.
Digital Fault Injection Attack Detector
In cryptography, an attack can be performed by injecting one or several faults into a device thus disrupting the functional behav…
Cyber Escort Unit IP: Bridging Software and Hardware Security Gaps
The Cyber Escort Unit is designed to fill the security gap between software cyber security and hardware by escorting step by step…
Attacks on digital circuits can occur when an attacker attempts to physically alter the device's internal components.
SHA IP Core with native SHA2-256 HMAC support
The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4.
The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea.
Programmable Root of Trust with Quantum Safe Cryptography acceleration
The CryptoManager RT-6xx v3 Root of Trust family is the latest generation of fully programmable FIPS 140-3 compliant hardware sec…
Advanced Encryption Standard Module
The CC-AES-AXI is a synthesisable Verilog model of a Encryption Standard module.
The ChaCha-IP-13 (EIP-13) is an IP solution for accelerating the ChaCha20 cipher algorithm (RFC7539), supporting the NIST CTR mod…
Memory & Bus Protection IP Core
The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
The Arm® SecurCore® SC300 processor is designed specifically for high-performance smartcard and embedded security applications.
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations…