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Compare 199 IP for TSMC from 15 vendors (1 - 10)
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  • 6nm
  • LPDDR6/5X/5 PHY V2 - TSMC N6
    • The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
    • With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
    • LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
    • The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications
    Block Diagram -- LPDDR6/5X/5 PHY V2 - TSMC N6
  • 12-bit, 5 MSPS ADC with 8:1 Input Mux in a TSMC 6nm
    • The ODT-ADS-12B5M-6T is an ultra-low-power, high-linearity ADC with rail-to-rail inputs designed in a TSMC 6nm process.
    • This 12-bit, 5MSPS ADC supports input signals up to 1 MHz and features excellent static and dynamic performance.
    • The input front-end includes a mux that can support 16 single-ended or differential inputs.
    Block Diagram -- 12-bit, 5 MSPS ADC with 8:1 Input Mux in a TSMC 6nm
  • Voltage & Current Reference Generator in TSMC 6/7nm FFC
    • The ODT-REF-6T is a reference current and voltage generator. This block includes a VREF/R circuit to create programmable voltages and currents.
    • ODT-REF-6T requires a constant 0.6V voltage input (ideally derived from a bandgap) in order to generate the required signals.
    Block Diagram -- Voltage & Current Reference Generator in TSMC 6/7nm FFC
  • 12 bit 250MSPS ADC on TSMC 7nm
    • The ODT-ADS-12B250M-7T is an ultra-low power ADC designed in a 7nm CMOS process.
    • This 12-bit, 250MSPS ADC supports input signals up to 100MHz and features a differential full-scale range of 0.8Vpp and excellent static and dynamic performance.
    Block Diagram -- 12 bit 250MSPS ADC on TSMC 7nm
  • PVT Sensor Subsystem
    • Start-up time: Typ 20us 
    • Current consumption: Max 25uA 
    • Industry standard digital interface 
    • Fully integrated macro 
    • Standard AMBA APB interface
    Block Diagram -- PVT Sensor Subsystem
  • NVM OTP XBC TSMC N6 1.8V
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N6 1.8V
  • All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (sub 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 7mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
  • Low Power All Digital Fractional-N PLL in TSMC N6/N7
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in TSMC N6/N7
  • Low Power All Digital Fractional-N PLL in Samsung 8LPP
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in Samsung 8LPP
  • USB4 PHY - TSMC N6 1.8V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    Block Diagram -- USB4 PHY - TSMC N6 1.8V, North/South Poly Orientation
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