Chiplet and D2D IP for TSMC
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- 6nm
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Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N6 X16, North/South (vertical) poly orientation
- 16-lane TX and RX square macros for placement in any edge of the die
- Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
- Implements NRZ and PAM-4 signaling
- Meets the performance, efficiency, and reliability requirements of die-to-die interconnects
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UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
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UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
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Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
- Offers leading performance, power, and area / beachfront per terabit
- Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
- Targeting the OIF XSR standards: CEI-112G and CEI-56G
- Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
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UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange