Simplifying Debug of Memory Models
Synopsys VC VIP provides Verdi Protocol Analyzer, a protocol and memory aware debug environment . In my previous blog Debugging Memory Protocols with the Verdi Protocol Analyzer, I discussed the value add for using the Verdi Protocol Analyzer to debug memory protocols easily and efficiently. Also, I described how easy it is to look at a specific command as a transaction rather than as interpreted signals. In this blog I’m going to show another feature that makes Verdi Protocol Analyzer the tool of choice for debugging memory protocol issues and for validating proper system behavior. Furthermore, the tool can be used for verification of the command sequencer and the interaction between the DUT and the memory models. The feature, we are going to look at today, is synchronizing transactions to the corresponding signals.
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Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
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- Reduce Protocol Debug Time with Memory VIP
- How to Reduce Memory Model Debug Time
- Coverage Models - Filling in the Holes for Memory VIP
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