How to Reduce Memory Model Debug Time
September 27, 2019
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
At some point, you have most likely faced one of the following challenges while debugging a memory model (Timing Issues, Log Messages, Bank Stats, Layered Debug, etc..)
Synopsys Memory Model (VIP), together with Verdi increases your overall debugging productivity. Below are examples of how the tightly coupled debug solution will help to address some of the pain points:
To read the full article, click here
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Reduce Protocol Debug Time with Memory VIP
- Simplifying Debug of Memory Models
- How to Get Started with Model-Based Systems Engineering
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage