Reduce Protocol Debug Time with Memory VIP
September 23, 2019
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
If you have not already deployed Protocol Aware Debug capabilities, learn why these are recommended…
Key attributes of the Memory Protocol Aware Debug flow:
- Protocol-centric debug enables user to quickly understand protocol activity, identify bottlenecks and quickly find and debug unexpected behavior
- Error, warning and messaging annotation within the protocol view to quickly root cause
- Graphical view of transaction, bank states, memory content, and handshaking with immediate access to context specific detailed information
- Lock-step linking to simulator-trace views (waveforms) enabling easy debug at any level of abstraction
Synopsys Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC (for DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N), ONFi, SD, and SPI along with native integration and optimizations with our VCS and Verdi tools.
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Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related Blogs
- How to Reduce Memory Model Debug Time
- Synopsys CXL Protocol Verification Solutions Proven with Real World Vendor Devices at the CXL Compliance Test Event
- Interactive Debugging: Reduce Your Simulation Debug Turn-Around-Time
- Accelerate Debug Productivity of Complex Serial Protocols