Accelerating Memory Debug
February 12, 2015
Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays
Related Semiconductor IP
- ORAN IP core
- MIPI D-PHY RX+ (Receiver) IP
- MIPI D-PHY TX+ (Transmitter)
- LVDS Deserializer IP
- LVDS Serializer IP
Related Blogs
- PCIe: Accelerating Debug
- Simplifying Debug of Memory Models
- Reduce Protocol Debug Time with Memory VIP
- How to Reduce Memory Model Debug Time
Latest Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Chip Design Industry Reaches an AI Inflection Point
- Cadence Agentic AI Reduces SoC/System Engineering Time by Months
- How AgentEngineer™ Technology Will Transform Engineering Workflows
- UALink: Powering the Future of AI Compute