Accelerating Memory Debug
Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related Blogs
- PCIe: Accelerating Debug
- Simplifying Debug of Memory Models
- Reduce Protocol Debug Time with Memory VIP
- How to Reduce Memory Model Debug Time
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet