PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted?
The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitment to the accelerated development of PCIe 5.0.
PCIe 5.0 rev 0.7 is published and already out for membership review as of May. The big-ticket item is, of course, support for 32GT/s.
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Multi-port Switch
- PCIe 5.0 Controller with AXI
- PCIe 5.0 Controller
- PHY for PCIe 5.0 and CXL
- PCIe 5.0 Integrity and Data Encryption Security Module
Related Blogs
- PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up
- PCI Express 5 vs. 4: What's New? [Everything You Need to Know]
- Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
Latest Blogs
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach