Cadence IP
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117
IP
from 10 vendors
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10)
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Highly scalable performance for classic and generative on-device and edge AI solutions
- Flexible System Integration
- Scalable Design and Configurability
- Efficient in Mapping State-of-the-Art AI/ML Workloads
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224G-LR SerDes PHY enables 1.6T and 800G networks
- TSMC 3nm process
- Supports full-duplex 1.25 to 225Gbps data rates
- Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
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10Gbps Multi-Protocol PHY IP
- Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
- High-performance decision feedback equalization and adaptive CTLE
- Available in X1 through X10 lane configurations
- Bifurcation and inverse bifurcation support
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Universal Chiplet Interconnect Express (UCIe 1.0) Controller
- Package Flexibility
- Power Efficiency
- Low Latency
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Tensilica ConnX 110/120
- Certified ISO 26262:2018 ASIL-compliant
- VLIW parallelism issuing multiple concurrent operations per cycle
- 128-bit or 256-bit SIMD
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112G-ELR PAM4 SerDes PHY
- Interoperability
- Maximize beach front bandwidth
- Layout flexibility
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Ultralink Controller
- 1Tbps/mm unidirectional bandwidth
- Low power and low latency
- Easy routing and straightforward integration
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DDR5/4 PHY for Samsung
- Lowest latency for data-intensive applications
- Highest data rates with detailed system guidelines
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Tensilica ConnX B10/B20
- Single-instruction, multiple-data (SIMD) vector processing
- Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
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Denali Controller for GDDR6
- Compatible with GDDR6 devices compliant to JESD250a
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
