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Compare 197 IP from 14 vendors (1 - 10)
  • Simulation VIP for xSPI
    • xSPI Profile 1
    • SPI (Read Zero Latency), DUAL (1-1-2, 1-2-2), Quad (As per JESD251-A1), and Octal modes Data Rate: STR and DTR
    • Modes
    • SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes
    Block Diagram -- Simulation VIP for xSPI
  • Simulation VIP for UFS
    • Interfaces
    • DPDN I/F and RMMI I/F when used with UniPro VIP. CPort signaling pin I/F and CPort message using transactions
    • UTP Layer - UPIUs
    • NOP IN, NOP OUT, Query Request/ Response, Task Management Request/ Response, Command, Response, Data Out, Data In
    Block Diagram -- Simulation VIP for UFS
  • Simulation VIP for UCIE
    • Protocol Layer Features
    • Streaming mode
    • PCIe mode
    • Protocol FDI LSMs
    Block Diagram -- Simulation VIP for UCIE
  • Simulation VIP for Toggle NAND
    • Speed
    • Up to 200MHz or 400Mbps per DQ pin
    • Up to 600MHz or 1200Mbps per DQ pin (Version 3.0/4.0)
    • Bits per Cell
    Block Diagram -- Simulation VIP for Toggle NAND
  • Simulation VIP for TileLink
    • Channels
    • Drive, sample, and check the signals and operations on channels A and D for TL-UL/TL-UH conformance level and on channels A, B, C, D and E for TL-C conformance level
    • TL-UL
    • Support for TL-UL conformance level including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors and Byte lanes
    Block Diagram -- Simulation VIP for TileLink
  • Simulation VIP for SPI NAND
    • Operation Modes
    • Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) and serial mode 0 and mode 3
    • Pins
    • HOLD# and WP# Pins functionalities
    Block Diagram -- Simulation VIP for SPI NAND
  • Simulation VIP for SPI
    • Full Duplex
    • Simultaneous transfer from Manager and Subordinate
    • Variable Size Shift Registers
    • 8, 16, and 32-bit shift register for Tx and Rx
    Block Diagram -- Simulation VIP for SPI
  • Simulation VIP for SD CARD and SDIO
    • SD Card device standard
    • Speed Range A and B
    • Default Speed Range A and faster Range B support
    • PHY-LINK I/F
  • Simulation VIP for SAS
    • Device type
    • Initiator, Target, and Expander
    • Operating Modes
    • Supports all SAS speeds: 1.5, 3, 6, 12, 24Gb/s
    Block Diagram -- Simulation VIP for SAS
  • Simulation VIP for Q-SPI
    • Device Density
    • From 256Mb to 2Gb with frequency up to 166MHz
    • Operation Mode
    • Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) with single and double transfer rate (STR and DTR)
    Block Diagram -- Simulation VIP for Q-SPI
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Semiconductor IP