1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
August 16, 2017
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Multi-port Switch
- PCIe 5.0 Controller with AXI
- PCIe 5.0 Controller
- PHY for PCIe 5.0 and CXL
- PCIe 5.0 Integrity and Data Encryption Security Module
Related Blogs
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
- PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
- Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
- PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Latest Blogs
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach
- UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC
- RISC-V for Infrastructure: For Now, It’s All About the Developer
- Unlock Your AI Potential: A Deep Dive into BrainChip’s Akida™ Cloud
- Breaking the Silence: What Is SoundWire‑I3S and Why It Matters