PCIe 5.0 Controller

Overview

The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0 and 3.1/3.0. A PCIe 5.0 Controller with AXI is also available. The controller delivers high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence/machine learning (AI/ML), data center, edge, 5G infrastructure and graphics.

How the PCIe 5.0 Controller Works

The PCIe 5.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 5.0, 4.0 and 3.1/3.0 specifications, as well as the version 5.x of the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

The vendor integrates and validates the PCIe 5.0 Controller with the customer’s choice of 3^rd-party PCIe 5.0 PHY.

Key Features

PCI Express layer
- Comprises complete PCIe 5.0 interface subsystem with Rambus PCIe 5.0 PHY
- Supports the PCI Express 5.0 rev. 1.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 5.x (8, 16, 32 and 64-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
- Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, DOE, CMA over DOE, and other optional features and ECNs
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
User Interface layer
- 512-bit or 256-bit transmit/receive low-latency user interface
- Up to 2 TLP per clock cycle in TLP Bypass mode (TLP chaining)
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Integrity and Data Encryption (IDE)
- Implements the PCI Express IDE ECN
- Configurable IDE engine
  - Supports x1 to x16 lanes
  - 256-bit or 512-bit data bus for PCIe IDE
- Configurable pipeline stages for difference process nodes for best cost and performance balance
- Supports containment and skid modes
- Supports multi-stream
- Utilizes high-performance AES-GCM for encryption, decryption, authentication
- PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
- PCIe IDE automatic IDE prefix insertion and detection
- PCIe IDE automatic IDE sync/fail message generation
- PCRC calculation & validation
- Efficient key control/refresh
- Bypass mode

Benefits

20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6200 customers , including several hundred of ASIC tape-outs
Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
Availability for PCIe 5.0 early adopters
Root-port, Endpoint, Dual-mode, Switch port in depth flexible configuration
Support for advanced Low Power states enables lower power consumption in energy-conscious applications
Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
Extensive data integrity features provide data protection on entire data path for storage and other data critical applications
Acclaimed global 24/5 support
Dedicated Advanced Design & Integration (ADI) team available to help withb development, integration, and verification

Block Diagram

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

Verilog RTL,
Supporting Documentation

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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