PCIe 5.0 Multi-port Switch

Overview

Key Features

• PCI Express Interfaces (upstream and downstream ports)
  • 1 upstream port, up to 31 downstream ports
  • Up to x16 link width per port
  • Link rate of 2.5, 5.0, 8.0, 16, and 32 Gbps per lane (Gen1, Gen2, Gen3, Gen4, Gen5 rates)
  • Supports PCI Express Base Specification Revision 5.0, and is compliant with the PCIe 4.0 and PCIe 3.1 Specifications at 16 GT/s, 8 GT/s and 5 GT/s
  • PHY Interface for PCI Express (PIPE) 5.x compliant
  • Single Virtual Channel (VC) implementation
  • Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit) for embedded endpoints
  • Configurable Receive and Replay buffer sizes
  • Advanced Error Reporting (AER) supported on each port
  • ECRC generation and check
  • ARI supported
  • Lane reversal supported
  • Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port 
  • Switch upstream port supports multiple physical functions
  • Support for Hot Plug on every downstream port
  • Access Control Services (ACS) supported
  • Optimized Buffer Flush/Fill (OBFF) supported
• Switching Logic
  • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
  • L1 and wake-up events forwarding
  • Peer-to-Peer transactions support between downstream ports
  • Broadcast and Multicast supported
  • Downstream Port Containment (DPC) supported
  • Round-Robin arbitration
  • No Packet buffering (cut-through architecture) for reduced latency
  • Built-in advanced data protection including ECRC, LCRC, ECC and Parity
  • Test port available for switch logic monitoring
  • Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic

Benefits

• Flexibility: The solution is highly configurable and scalable. For example, the designer can choose to implement up to 32 external or embedded Endpoints, and define for each port a different clock speed, data rate and throughput in order to optimize the footprint of the design.
• 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 5700 customers , including several hundred of ASIC tape-outs.
• Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
• Significant Latency, Power and Performance Improvements: XpressSWITCH delivers improvements in latency (using Cut-Through mode), optimization of power consumption (using embedded Endpoints), and better performance through a non-blocking architecture (using Peer-to-Peer transfers between Endpoints).
• Demonstrated reliability: The solution has been integrated, tested and demonstrated on PLDA’s XpressKUS FPGA board running a Xilinx® Kintex® UltraScale™ device and has achieved PCI Express (PCIe®) compliance.
• No requirement for software development: The switch will work without additional software development through the use of the configuration wizards and reference designs provided, reducing time-to-market
• BOM/Cost savings: PCIe Embedded Switch IP enables a minimized footprint and reduces the number of chips required on the board.
• Shorter time-to-market: PCIe Embedded Switch IP enables the reuse of existing design, reducing design time and creating independence from the SerDes Technology.

Block Diagram

Applications

• HPC,
• Cloud Computing,
• AI,
• Machine Learning,
• Enterprise,
• Networking,
• Automotive,
• AR/VR,
• Test and Measurement

Deliverables

• Verilog RTL,
• Supporting Documentation

Technical Specifications