PCIe 5.0 Multi-port Switch

Overview

The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports.

How the PCIe 5.0 Multi-Port Switch Works

The PCIe 5.0 Switch IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs. It enables designers to use fewer PHYs, saving latency, power consumption and costs.

The PCIe 5.0 Multi-Port Swtich has been extensively verified using commercial and internally developed VIP and test suites. It is PCI-SIG certified since 2016 and is often used as an interoperability host platform for PCIe compliance testing.

Key Features

PCI Express Interfaces (upstream and downstream ports)
- 1 upstream port, up to 31 downstream ports
- Up to x16 link width per port
- Link rate of 2.5, 5.0, 8.0, 16, and 32 Gbps per lane (Gen1, Gen2, Gen3, Gen4, Gen5 rates)
- Supports PCI Express Base Specification Revision 5.0, and is compliant with the PCIe 4.0 and PCIe 3.1 Specifications at 16 GT/s, 8 GT/s and 5 GT/s
- PHY Interface for PCI Express (PIPE) 5.x compliant
- Single Virtual Channel (VC) implementation
- Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit) for embedded endpoints
- Configurable Receive and Replay buffer sizes
- Advanced Error Reporting (AER) supported on each port
- ECRC generation and check
- ARI supported
- Lane reversal supported
- Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port
- Switch upstream port supports multiple physical functions
- Support for Hot Plug on every downstream port
- Access Control Services (ACS) supported
- Optimized Buffer Flush/Fill (OBFF) supported
Switching Logic
- PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
- L1 and wake-up events forwarding
- Peer-to-Peer transactions support between downstream ports
- Broadcast and Multicast supported
- Downstream Port Containment (DPC) supported
- Round-Robin arbitration
- No Packet buffering (cut-through architecture) for reduced latency
- Built-in advanced data protection including ECRC, LCRC, ECC and Parity
- Test port available for switch logic monitoring
- Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic

Benefits

Fully transparent design eliminates the need for Host configuration and management software
Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
Lowest latency switching logic on the market (2 clock cycles)
Architecture allows insertion of custom processing in-the-flow (i.e. filtering, encryption, etc.)
The only solution that supports Hot Plug

Block Diagram

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

IP files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
Documentation
PCI Express Bus Functional Model
- Encrypted Simulation libraries
Software
- PCI Express Windows x64 and Linux x64 device drivers
- PCIe C API
Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & DC constraint files (ASIC)
- Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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