PCI Express 5 vs. 4: What's New? [Everything You Need to Know]
Introduction
What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications.
Want to know the best part in terms of feeds and speeds?
We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link bandwidth of almost 128 Gigabytes per second (GBps).
Impressive, isn’t it?
It is, because this speed boost is needed to support a new generation of artificial intelligence (AI) and machine learning (ML) applications as well as cloud-based workloads.
Want to know a little more about AI/ML applications and cloud-based workloads?
Both are significantly increasing network traffic. In turn, this is accelerating the implementation of higher speed networking protocols which are seeing a doubling in speed approximately every two years.
So, we’ve taken a quick look at feeds and speeds, but what else does PCIe 5 bring to the table?
You can find everything you need to know in the article below.
Let’s dive right in.
Related Semiconductor IP
- PCI Express (PCIe) 2.1 Controller
- PCI Express 4.0 PHY
- PCI Express - Configurable PCI Express 4.0 IP
- PCI Express Gen 4 PHY
- PCIe 1.1 Controller with PHY Interface for PCI Express (PIPE) specification and native user interface support
Related Blogs
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
- Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth - Visit Cadence at PCI-SIG DevCon 2015
- CCIX Protocol Push PCI Express 4.0 up to 25G
- Doubling Bandwidth in Under Two Years: PCI Express Base Specification Revision 5.0, Version 0.9 is Now Available to Members
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?