Opening an FPGA-Based MIPS CPU Core to Universities
Imagination's MIPSfpga program is designed to bring a new CPU architecture education paradigm to universities around the world.
"Education, education, education" -- a simple slogan, but one that worked, and one that has contemporary implications for the electronics industry owing to the on-going shortage of newly-qualified electronics engineers, along with the concern that those new graduates are often not fully-equipped with the necessary skills to be useful to the companies that employ them.
In the area of CPU design, however, engineering students are getting a significant boost. One company has just made the unusual decision to give something to colleges and universities around the globe that will help students gain a better understanding of the fundamentals of programmable electronics.
In April this year, Imagination Technologies -- most famous for its flagship products: PowerVR and MIPS -- made a revolutionary announcement: as part of its university program, the company would start offering free and open access to a fully-validated, current-generation MIPS CPU in a complete teaching package.
To read the full article, click here
Related Semiconductor IP
- Configurable CPU tailored precisely to your needs
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
- RISC-V CPU IP
- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
Related Blogs
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- An Elephant on a Diet
- It's an Android Ice Cream Sandwich Tablet, and it's MIPS!
- The CEVA-MM3101: An Imaging-Optimized DSP Core Swings for an Embedded Vision Home Run
Latest Blogs
- The Memory Imperative for Next-Generation AI Accelerator SoCs
- Leadership in CAN XL strengthens Bosch’s position in vehicle communication
- Validating UPLI Protocol Across Topologies with Cadence UALink VIP
- Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology
- LPDDR6 vs. LPDDR5 and LPDDR5X: What’s the Difference?