CPU IP

• The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no local host processor.
• The DB-I3C-S-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
• The DB-I3C-S-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec ver1_0 specification.

• The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock.
• The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
• The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.

• 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications

Arm Neoverse V3AE is the perfect platform for developing complex automated driving and ADAS vehicle systems.

• The Fastest Neoverse CPU Ever
• A Platform Built for AI
• Next-Generation Security

• Optimized Performance per Watt Efficiency
• Performance and Power Efficiency for AI and ML Workloads
• Arm’s Most Scalable Platform

• Aggressive eight-wide deep out-of-order pipeline
• Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2

• Five-stage pipeline
• Harvard architecture
• RV32I Base RISC-V ISA

• Five-stage pipeline
• Harvard architecture
• RV64I Base RISC-V ISA

• NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic.
• Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance.