CPU IP

• Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
• With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.

• Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RVV1.0 and supports all extensions of Vector Crypto.
• With a score of 8.5 SPECInt2006/GHz, Dubhe-83 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.

• The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no local host processor.
• The DB-I3C-S-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
• The DB-I3C-S-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec ver1_0 specification.

• The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock.
• The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
• The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.

• 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications

Arm Neoverse V3AE is the perfect platform for developing complex automated driving and ADAS vehicle systems.

• The Fastest Neoverse CPU Ever
• A Platform Built for AI
• Next-Generation Security

• Optimized Performance per Watt Efficiency
• Performance and Power Efficiency for AI and ML Workloads
• Arm’s Most Scalable Platform

• Fully compliant with the RVA23 RISC-V specification
• Comparable PPA to Arm Neoverse V3 / Cortex-X4
• Standard AMBA CHI.E coherent interface for SoC and chiplet integration
• Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations

• Five-stage pipeline
• Harvard architecture
• RV64I Base RISC-V ISA